A1211LUA-T【PDF 5/14 页】IC LATCH HALL EFFECT 3-SIP

Continuous-Time Latch Family

A1210, A1211,

A1212, A1213,

and A1214

5

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information

Characteristic

Symbol

Test Conditions

Value Units

Package Thermal Resistance

R

窲A

Package LH, on single layer, single-sided PCB with copper

limited to solder pads

228 篊/W

Package LH, on single layer, double-sided PCB with 0.926 in

2

copper area

110 篊/W

Package UA on single layer, single-sided PCB with copper

limited to solder pads

165 篊/W

6

7

8

9

2

3

4

5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

20 40 60 80 100 120 140 160 180

T

J(max)

= 165篊; I

CC

= I

CC(max)

Power Derating Curve

(R

窲A

= 228 篊/W)

Minimum-K PCB, Package LH

(R

窲A

= 110 篊/W)

Low-K PCB, Package LH

(R

窲A

= 165 篊/W)

Minimum-K PCB, Package UA

V

CC(min)

V

CC(max)

0

100

200

300

400

500

600

700

800

900

1000

1100

1200

1300

1400

1500

1600

1700

1800

1900

20 40 60 80 100 120 140 160 180

Temperature (癈)

Power Dissipation versus Ambient Temperature

(

R

?/DIV>

J

A

=

1

6

5

?/DIV>

C

/

W

)

M

i

n

i

m

u

m

-

K

P

C

B

,

P

a

c

k

a

g

e

U

A

(

R

?/DIV>

JA

=

2

8

?/DIV>

C

/

W

)

M

i

n

im

u

m

-K

P

C

B

,

P

a

c

k

a

g

e

L

H

(

R

?/DIV>

J

A

=

1

0

?/DIV>

C

/

W

)

L

o

w

-

K

P

C

B

,

P

a

c

k

a

g

e

L

H

110

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